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STMicroelectronicsTransistor Type
NPN
Maximum Continuous Collector Current
500 mA
Maximum Collector Emitter Voltage
50 V
Maximum Emitter Base Voltage
50 V
Package Type
PDIP
Mounting Type
Through Hole
Pin Count
18
Transistor Configuration
Common Emitter
Number of Elements per Chip
8
Minimum DC Current Gain
1000
Maximum Collector Emitter Saturation Voltage
1.1 V
Minimum Operating Temperature
-20 °C
Maximum Operating Temperature
+85 °C
Length
23.24mm
Height
3.93mm
Width
7.1mm
Dimensions
23.24 x 7.1 x 3.93mm
Detalji o proizvodu
Darlington Transistor Arrays, STMicroelectronics
Darlington transistor power drivers are high-voltage, high-current switch arrays containing multiple open-collector Darlington pairs and integral suppression diodes for inductive loads. The high current rating of each output is 500 mA or higher. The inputs are pinned opposite the outputs in the IC package to simplify the application board layout. The interface is standard logic level for TTL or CMOS.
Darlington Transistor Drivers
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Proizvodno pakiranje (cijev)
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P.O.A.
Proizvodno pakiranje (cijev)
5
Tehnička dokumentacija
Tehnički podaci
Proizvođač
STMicroelectronicsTransistor Type
NPN
Maximum Continuous Collector Current
500 mA
Maximum Collector Emitter Voltage
50 V
Maximum Emitter Base Voltage
50 V
Package Type
PDIP
Mounting Type
Through Hole
Pin Count
18
Transistor Configuration
Common Emitter
Number of Elements per Chip
8
Minimum DC Current Gain
1000
Maximum Collector Emitter Saturation Voltage
1.1 V
Minimum Operating Temperature
-20 °C
Maximum Operating Temperature
+85 °C
Length
23.24mm
Height
3.93mm
Width
7.1mm
Dimensions
23.24 x 7.1 x 3.93mm
Detalji o proizvodu
Darlington Transistor Arrays, STMicroelectronics
Darlington transistor power drivers are high-voltage, high-current switch arrays containing multiple open-collector Darlington pairs and integral suppression diodes for inductive loads. The high current rating of each output is 500 mA or higher. The inputs are pinned opposite the outputs in the IC package to simplify the application board layout. The interface is standard logic level for TTL or CMOS.