Tehnička dokumentacija
Tehnički podaci
Maximum Output Frequency
346MHz
Number of Elements per Chip
4
Mounting Type
Surface Mount
Minimum Output Frequency
2kHz
Package Type
QFN
Maximum Supply Current
279 mA
Pin Count
36
Maximum Input Frequency
710MHz
Dimensions
6 x 6 x 0.85mm
Height
0.85mm
Length
6mm
Maximum Operating Supply Voltage
3.63 V
Maximum Operating Temperature
+85 °C
Minimum Operating Supply Voltage
2.97 V
Minimum Operating Temperature
-40 °C
Width
6mm
Zemlja podrijetla
Taiwan, Province Of China
Detalji o proizvodu
Si531x/2x/6x/7x Jitter Attenuators, Silicon Labs
The Silicon Labs Si531x/2x/6x/7x jitter attenuators generate any combination of output frequencies from any input frequency. Using the Silicon Labs third-generation DSPLL architecture they simplify your clock tree design by replacing multiple clocks and oscillators. Minimising your BOM count and complexity.
Informacije o stanju skladišta trenutno nisu dostupne.
Proverite ponovno kasnije.
RSD 7.773
komad (isporučivo u traci) (bez PDV-a)
RSD 9.327
komad (isporučivo u traci) (s PDV-om)
1
RSD 7.773
komad (isporučivo u traci) (bez PDV-a)
RSD 9.327
komad (isporučivo u traci) (s PDV-om)
1
Kupujte na veliko
količina | Jedinična cena |
---|---|
1 - 4 | RSD 7.773 |
5+ | RSD 7.250 |
Tehnička dokumentacija
Tehnički podaci
Maximum Output Frequency
346MHz
Number of Elements per Chip
4
Mounting Type
Surface Mount
Minimum Output Frequency
2kHz
Package Type
QFN
Maximum Supply Current
279 mA
Pin Count
36
Maximum Input Frequency
710MHz
Dimensions
6 x 6 x 0.85mm
Height
0.85mm
Length
6mm
Maximum Operating Supply Voltage
3.63 V
Maximum Operating Temperature
+85 °C
Minimum Operating Supply Voltage
2.97 V
Minimum Operating Temperature
-40 °C
Width
6mm
Zemlja podrijetla
Taiwan, Province Of China
Detalji o proizvodu
Si531x/2x/6x/7x Jitter Attenuators, Silicon Labs
The Silicon Labs Si531x/2x/6x/7x jitter attenuators generate any combination of output frequencies from any input frequency. Using the Silicon Labs third-generation DSPLL architecture they simplify your clock tree design by replacing multiple clocks and oscillators. Minimising your BOM count and complexity.