Nexperia 74HC238D,653, Decoder, 16-Pin SO

The 74HC238, 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '238 ICs and one inverter.

• Multiple input enable for easy expansion or independent controls
• Integrated input latch to store the address of decoder lines
• Ideal for memory chip select decoding
• Asynchronous and synchronous load options
• Overvoltage tolerant input options
• Inverting and non-inverting output options
• 3-stage outputs
• High frequency
• Can be cascaded
• Key applications
• Selection of memory banks and peripherals
• I/O expansion