Nexperia 74LVC138APW,118, Decoder, 16-Pin TSSOP

The 74LVC138A is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected. There are three enable inputs: two Active LOW (E1 and E2) and one Active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four 74LVC138A devices and one inverter.

• Multiple input enable for easy expansion or independent controls
• Integrated input latch to store the address of decoder lines
• Ideal for memory chip select decoding
• Asynchronous and synchronous load options
• Overvoltage tolerant input options
• Inverting and non-inverting output options
• 3-stage outputs
• High frequency