Tehnička dokumentacija
Tehnički podaci
Proizvođač
onsemiProduct Type
18 Bit D Type Latch
Logic Family
4000
Latch Mode
Transparent
Logic Function
RS-Latch
Number of Channels
4
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface
Minimum Supply Voltage
-5V
Package Type
SOIC
Pin Count
16
Maximum Supply Voltage
18V
Minimum Operating Temperature
-55°C
Maximum Operating Temperature
125°C
Length
10mm
Height
1.5mm
Standards/Approvals
No
Series
4000B
Automotive Standard
AEC-Q100
Detalji o proizvodu
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.
Informacije o stanju skladišta trenutno nisu dostupne.
€ 23,04
€ 0,48 komadno (u cijevi od 48) (bez PDV-a)
48
€ 23,04
€ 0,48 komadno (u cijevi od 48) (bez PDV-a)
Informacije o stanju skladišta trenutno nisu dostupne.
48
| količina | jedinična cijena | Po cijev |
|---|---|---|
| 48 - 432 | € 0,48 | € 23,04 |
| 480 - 912 | € 0,35 | € 16,80 |
| 960+ | € 0,31 | € 14,88 |
Tehnička dokumentacija
Tehnički podaci
Proizvođač
onsemiProduct Type
18 Bit D Type Latch
Logic Family
4000
Latch Mode
Transparent
Logic Function
RS-Latch
Number of Channels
4
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface
Minimum Supply Voltage
-5V
Package Type
SOIC
Pin Count
16
Maximum Supply Voltage
18V
Minimum Operating Temperature
-55°C
Maximum Operating Temperature
125°C
Length
10mm
Height
1.5mm
Standards/Approvals
No
Series
4000B
Automotive Standard
AEC-Q100
Detalji o proizvodu
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.