STMicroelectronics Evaluation Board MCU Evaluation Board STM32F769I-EVAL

Evaluation Board with STM32F769NI Microcontroller

The STM32 evaluation boards have been designed as a complete demonstration and development platform for the series of ARM Cortex STM32 MCUs. The STM32F769I-EVAL includes high-speed embedded memories, and an extensive range of interfaces to evaluate all the peripherals and to help developing applications. A daughterboard can also be connected for specific applications. The integrated ST-LINK/V2-1 provides an embedded in-circuit debugger and programmer for the STM32. This evaluation board can be used as a reference design for user application development but it is not considered as a final application.

Features

• 2 MB of Flash memory, 512 KB of SRAM, 16 KB instruction TCM RAM (for critical real-time routines) and 4 KB backup SRAM
• 4 in (101.6 mm) 800 x 480 capacitive touch LCD display with MIPI DSI connector
• 4-color user LEDs
• Joystick with 4-direction control and selector
• Camera module
• Flexible external memory controller: 8M x 32-bit SDRAM, 1M x 16-bit SRAM and 8M x 16-bit NOR Flash
• Serial Audio Interface (SAI) audio codec
• Stereo digital microphone
• Stereo speaker outputs
• Four I2 C interfaces
• Real-time clock with backup battery
• “Reset”, “Wake Up/Tamper” or key button
• 512-Mbit Quad-SPI NOR Flash
• 2 GB (or more) SDIO interface micro-SD card
• 2Gx16-bit NAND Flash interface to connect NAND Flash module
• USB OTG HS and FS with Micro-AB connectors
• IEEE-802.3-2002 compliant Ethernet connector
• Six 5 V power supply options: power jack, ST-LINK/V2-1 Micro-B USB connector, User USB HS connector, User USB FS1 connector, User USB FS2 connector, daughterboard
• CAN2.0 A/B compliant connection
• RS-232 DB9 communication
• JTAG/SWD and ETM trace debug support, ST-LINK/V2-1 embedded
• Extension and memory connectors for daughterboard or wrapping board
• Potentiometer and motor control connector

The STM32F7 microcontrollers feature ST’s ART Accelerator™ as well as an L1 cache and deliver the maximum theoretical performance of the ARM Cortex-M7 core, regardless if code is executed from embedded Flash or external memory. Typical performance figures: 1082 CoreMark / 462 DMIPS at 216MHz clock frequency.

• AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories
• Double-Precision Floating-Point maths unit on some variants
• Up to 16KB +16KB of I-cache and D-cache
• Up to 2MB of embedded Flash memory, with Read-While-Write capability on certain devices
• Up to 512KB of data memory, including up to 128KB of Tightly-Coupled Memory for Data (DTCM) for Stacks, Heaps
• 16KB of Tightly-Coupled Memory for Instructions (ITCM) for time-critical routines
• 4KB of backup SRAM to keep data in the lowest power modes
• Peripheral speed is independent from CPU speed (dual clock support)
• Protected code execution feature (PC-ROP) on some variants
• Power Efficiency: 7 CoreMark/mW at +1.8Vdc